1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatus for testing integrated circuits.
2. Description of the Background Art
Some applications call for the placement of multiple integrated circuits in one package. For example, several dies of integrated circuits may be mounted on a single substrate, which is then encapsulated using plastic or ceramic packaging technology. Putting multiple integrated circuits in one package advantageously minimizes printed circuit board space requirements, and facilitates manufacture of custom devices by combining several off-the-shelf integrated circuits. A single package having multiple integrated circuits is also referred to as a multi-chip module.
Multi-chip modules present unique testing problems because embedded integrated circuits may no longer be directly accessible after the packaging process. After packaging, some pads of a die may no longer be able to receive signals from outside the multi-chip module because those pads are connected exclusively to another embedded die. Those pads may also be test pads that are not routed to an external pin of the multi-chip module in order to minimize pin count.
Because of difficulties in testing multi-chip modules, some vendors individually test integrated circuits before packaging them together. Once packaged, the integrated circuits are assumed to be good and not extensively tested. This approach ignores the fact that an integrated circuit may fail during the packaging process (and anytime before it leaves the factory).
Assembled printed circuit boards and multi-chip modules can be tested using the IEEE 1149.1 standard. The IEEE 1149.1 includes guidelines for boundary scan testing, which is useful in verifying the structural integrity of pin-to-pin connections between integrated circuits mounted on a printed circuit board or multi-chip module. However, the serial nature of IEEE 1149.1 results in relatively long test time and cost. The IEEE 1149.1 also does not take advantage of the testability of individual integrated circuits before they were packaged together in a multi-chip module.
The present invention relates to methods and apparatus for testing multiple integrated circuits in a single package.
In one embodiment, a test circuit is coupled to receive a signal from a signal generator such as a test equipment. The test circuit allows access to one or more terminals of a first integrated circuit, a second integrated circuit, or both based at least on the signal. The test circuit may be in the first integrated circuit. The first integrated circuit and the second integrated circuit may be in a single package.
In one embodiment, the test circuit routes signals to and from the second integrated circuit, thus allowing the second integrated circuit to be tested as if it was stand-alone.
In one embodiment, the test circuit allows access to otherwise inaccessible terminals of the first integrated circuit, the second integrated circuit, or both.
These and other features and advantages of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.